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STUDY GUIDE · GKU 3

Digital design study guide (Computer Engineering)

This unit builds hardware from bits upward. It starts with how numbers and characters are written in binary, then Boolean algebra and Karnaugh maps for making logic small, then the standard combinational blocks (multiplexers, decoders, adders) and the storage elements (latches, flip-flops, registers, counters). The second part puts them together the way a processor is built: a datapath that moves and transforms data, a state machine that sequences it, the timing that decides how fast the clock can run, and the HDL that describes it all for synthesis. Exam questions here are short and exact — a conversion, a minimal expression, a counter state, a maximum clock frequency — so every section ends with worked numbers.

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Structured by the official ETEC subject standard for this topic: every listed topic and learning outcome, with formulas, figures and worked examples. The full sections are available to members in the app.

SKU 3.1 · Boolean algebra and design of logic circuits

  1. Number systems, fixed point and character codes

    Converting integers and fractions between decimal, binary and hexadecimal; signed integers in two's complement; fixed-point numbers; and how ASCII and Unicode (UTF-8, UTF-16) turn text into bytes.

  2. Boolean algebra and two-level gate networks

    The basic and derived operations, the laws used to simplify an expression by hand, canonical sum-of-products and product-of-sums forms, and how a two-level expression becomes AND-OR, OR-AND, NAND-NAND or NOR-NOR hardware under positive, negative or mixed logic.

  3. Karnaugh maps and minimal two-level logic

    How a Karnaugh map turns algebraic simplification into grouping adjacent cells, how to find prime and essential prime implicants, how to use don't-cares, and how to prove that an answer is minimal.

  4. Multiplexers, demultiplexers, decoders and encoders

    The four routing blocks every datapath is built from: what each does, its equation, how to build a wide one from narrow ones, and how a multiplexer or a decoder implements an arbitrary Boolean function.

  5. Adders, subtractors, shifters and comparators

    The arithmetic building blocks of an ALU: half and full adders, the ripple-carry adder and its delay, subtraction and overflow in two's complement, logical and arithmetic shifts, and equality and magnitude comparators.

  6. Latches and flip-flops

    How feedback stores a bit: the SR and D latches, the edge-triggered D flip-flop, the JK and T flip-flops with their characteristic and excitation tables, and the setup, hold and clock-to-Q times that every synchronous design depends on.

  7. Registers, shift registers and counters

    Groups of flip-flops that hold words, move bits serially, and count: the load-enable register, serial and parallel shift registers, ripple and synchronous binary counters, modulo- counters, and ring and Johnson counters.

SKU 3.2 · Control and datapath design

  1. Datapaths, control signals and synchronous timing

    How a digital system is split into a datapath (registers, ALU, multiplexers) and a controller that sequences it, written in register-transfer notation; and the timing analysis that sets its clock: setup and hold checks, clock skew, maximum frequency, and pin-level setup, clock-to-out and pin-to-pin delays.

  2. Finite state machines: Moore and Mealy

    From a word description to hardware: state diagram, state table, state encoding (binary, Gray, one-hot), next-state and output equations, and the difference between Moore and Mealy machines, worked through on a sequence detector.

  3. Algorithmic state machines, control units and HDL

    ASM charts as a precise way to draw a controller and its register transfers, the control unit of a simple processor as an ASM, and how the same design is written in Verilog at register-transfer level, simulated, synthesised and timed on programmable logic.

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