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STUDY GUIDE · GKU 2

Computer architecture and organization study guide (Computer Engineering)

This unit opens the processor. It starts with the stored-program machine, the instructions it understands and how a line of C becomes those instructions; then how numbers are held in a fixed number of bits and where that breaks; then how to measure speed honestly. The second half is about making the machine fast: pipelining, the memory hierarchy and caches, virtual memory, and the interrupts and serial links that connect it to the outside world. Most exam questions here are short calculations — a field width, a CPU time, a pipeline cycle count, a cache address split — so every section ends with worked numbers.

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Structured by the official ETEC subject standard for this topic: every listed topic and learning outcome, with formulas, figures and worked examples. The full sections are available to members in the app.

SKU 2.1 · Instruction set architecture and computer arithmetic

  1. The von Neumann machine, the instruction cycle and addressing modes

    The functional units of a stored-program computer, the fetch–decode–execute cycle as register transfers, the classes of instructions, and how each addressing mode finds its operand.

  2. Assembly language and program translation

    Hand-translating C statements into RISC-V assembly (expressions, arrays, loops), and what the compiler, assembler, linker and loader each do on the way to a running program.

  3. RISC compared with CISC

    Two philosophies of instruction-set design, what each trades in the CPU-time equation, and why modern x86 processors are RISC machines on the inside.

  4. Number representation: range, precision and overflow

    Unsigned and two's complement integers, when an addition overflows, and IEEE 754 floating point: what range and precision a format gives, and what underflow does.

  5. Computer performance metrics

    CPU time and the iron law, average CPI of an instruction mix, why MIPS misleads, benchmarks, and Amdahl's law for judging an arithmetic-unit upgrade or extra cores.

SKU 2.2 · Processor and memory organization

  1. Instruction-level parallelism: pipelining and hazards

    How a five-stage pipeline overlaps instructions, the speedup it can give, the structural, data and control hazards that cost stall cycles, and how forwarding and prediction recover most of them.

  2. Memory performance metrics

    Latency, cycle time and bandwidth of a memory, how interleaving overlaps accesses, and the average memory access time of a hierarchy with one or two cache levels.

  3. Cache memory organizations

    Direct-mapped, set-associative and fully associative caches; splitting an address into tag, index and offset; tracing hits and misses; replacement and write policies.

  4. Memory management and virtual memory

    Why each process gets its own virtual address space, how paging translates addresses through a page table, what the TLB saves, and what a page fault costs.

  5. Interrupts, I/O transfer and serial communication

    Polling, interrupts and DMA and what each costs the processor; vectored and prioritised interrupts; asynchronous against synchronous serial links; and why fast links became serial.

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