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STUDY GUIDE · GKU 2

Computer architecture and organization study guide (Computer Science)

A program is text; a computer is switches. This unit follows the path between them. It starts with how the hardware evolved to the multi-core chips of today, how logic gates are combined into adders, an ALU, registers and memory, and how integers, real numbers, characters and records are laid out in bits. It then shows how a von Neumann machine fetches and executes instructions, how high-level statements become assembly, how a pipeline overlaps instructions, and how subroutine calls and interrupts use the stack. It ends with the memory system — technologies, caches, virtual memory — and with I/O, buses and disks. Each section opens with a quick-revision card, and the worked examples run from easy to exam level; every number in them was recomputed in Python, the Python listings were run, the C struct sizes were compiled with clang, and the instruction counts of the assembly listings are counted from the listings as written.

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Structured by the official ETEC subject standard for this topic: every listed topic and learning outcome, with formulas, figures and worked examples. The full sections are available to members in the app.

SKU 2.1 · Digital logic and machine-level data representation

  1. Generations of computers, the power wall and multi-core

    What changed across the five generations of computers, why clock rates stopped rising, and how to compare single-core and multi-core designs with the CPU time equation and Amdahl's law.

  2. Logic gates, Boolean algebra and circuit minimisation

    From a truth table to a minimal circuit: Boolean laws, Karnaugh maps, NAND-only designs, and how the slowest path through the gates sets the speed.

  3. Adders, the ALU, registers and memory: building a processor

    How full adders become an ALU with status flags, how flip-flops become registers and decoders address memory, and how to judge whether a small processor circuit is correct and fast.

  4. Integers in binary: conversion, two's complement, shifts and overflow

    Converting between bases, reading one bit pattern as signed or unsigned, sign extension and arithmetic shifts, and deciding from the bits whether an addition overflowed.

  5. Floating point, characters, records and arrays in memory

    IEEE 754 single precision, ASCII and UTF-8 text with a small algorithm on characters, and how arrays and records are laid out — row-major addressing, alignment and padding.

SKU 2.2 · Machine organization at the assembly level

  1. The von Neumann machine and the instruction cycle

    The parts of a stored-program computer, the fetch–decode–execute cycle in register-transfer notation, a trace on an accumulator machine, and why one shared path to memory limits speed.

  2. Instruction formats, addressing modes and compiled code

    How an instruction word is divided into fields, how addressing modes find operands, how many addresses an instruction names, and how expressions, conditions, loops and arrays become assembly.

  3. Pipelining and instruction-level parallelism

    How overlapping instructions raises throughput, how hazards and stalls raise the CPI, how a two-bit predictor guesses branches, and what limits instruction-level parallelism.

  4. Subroutines, the stack and interrupts

    How CALL and RET use the stack, why nested calls need one, which registers a subroutine or an interrupt handler must save, and how vectored interrupts are dispatched and what they cost.

SKU 2.3 · Memory systems, interfacing and communication

  1. Memory technologies, the hierarchy and caches

    SRAM, DRAM, flash and ROM compared; why a hierarchy works; how a cache splits an address; tracing hits and misses; and the average access time and CPI that result.

  2. Virtual memory: translation, page tables and the TLB

    The hardware side of virtual memory: how the MMU splits and translates an address, how large a page table is, how the TLB speeds translation, and the two conventions for its effective access time.

  3. I/O transfers, buses and storage devices

    Polling, interrupt-driven I/O and DMA compared by the processor time they cost; the kinds of bus and when each fits; and the access time of a magnetic disk against an SSD.

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